#Allwinner h3 soc 64 Bit
#Allwinner h3 soc serial

ID 1f3a:efe8 Allwinner Technology sunxi SoC OTG connector in FEL/flashing mode I've started up the H5 without the SD card and can see that its present on the USB port in FEL mode: I've recompiled uart0-helloworld-sdboot.c as follow, without getting any compiler errors:Р”В¬ROSS_COMPILE=arm-none-eabi- make uart0-helloworld-sdboot.elf Therefore, the 32-bit bare-metal compiler (arm-none-eabi-gcc) should be used.

#Allwinner h3 soc 64 Bit

Some googling revealed that the 64 bit instruction set does not support the 'mcr' instruction.Р”Р„ bit of reading atР’В revealed that the core starts up in 32 bit mode and the BROM & u-boot is standard 32-bit code. I've taken a detour to compileР’В uart0-helloworld-sdboot.c using the 64-bit bare-metal compiler (aarch64-none-elf-gcc), but it fails on theР’В assembler instruction at

#Allwinner h3 soc serial

I assume my H5 (orangePi Zero+) and USB serial UART My u-boot is printing its boot log on UART0. I'm investigating secure boot as discussed here for the H3. I've successfully build u-boot, linux 5.1 and ubuntu 21.04 rootfs for the H5.

I'm trying to repeat the steps on the H5. Hi, Thank you for the great post on the H3. Board is stucked on booting of SPL image. Output: After writing TOC0 image into sdcard, insert the sdcard with board. $ sudo dd if=sunxi-spl.toc0 of=/dev/sdX bs=1024 seek=8 $ sudo dd if=/dev/zero of=/dev/sdX bs=1k count=1023 seek=1 $ ruby mktoc0.rb privkey.pem sunxi-spl.bin sunxi-spl.toc0Р”В¦. Using thatР’В mktoc0.rb script, convertedР’В spl image from bin format to TOC0 format. Change entry address of H6 from 0x0 to 0x20000 at line number 167, because entry address of H6 is 0x20000. Replace the '.sum' method with '.reduce(:+)' at line number 139Р”Сћ. NOTE: Before executing a script, following changes are required in mktoc0.rb.Р”РЋ. We used eFuseReaderr.c to read eFuse values. We read back all values to confirm whether they are written perfectly or not. This shouldn't be a problem as per LCJS format, I guess).Р”В¤. ( Note: At first we wrote 0x8000 by mistake in LCJS field and then we modified script to make it to 0x800. Now, We used fel_write_key.sh script to write rotpk hash (in little endian format) and secure bit into eFuse with help of 'sunxi-fel' using fel_write_key.sh script. We can also use your described method toР’В generate ROTPK. Using mkrotpk.rb script, computed SHA256 of public key. $ openssl rsa -in privkey.pem -pubout -out pubkey.pem // Public key We used the private key of generate public key from that. We also took care of addressing for H6 SoC.Р”РЋ. Hi Xeniter, Replying on behalf of Pratik. would double check if its not necessary to set them. So you need adjust at least the sid part of the script, also there some new efuses for changing boot order. How did you you written the key? could you post fel code?Р”Р„ssume the felscript to burn fuses will not work for H6 cause the sid register are now on 0x03006000 instead at 0x01C14000 (see ) Please help me out the problem, What i am doing wrong? Please find attachedР’В script and SPL image file. There are nothing to print on serial console. $ sudo dd if=unxi-spl.toco of=/dev/sdb bs=1024 seek=8Р”Р„fter performed the above steps on board, board is sucked on booting of SPL image. NOTE: UsedР’В entry address (run_addr = 0x20000) according to H6 SoC $ ruby gen_toc0.rb privatekey.pem sunxi-spl.bin sunxi-spl.toco Enable and write a SHA256 of public key into eFuse using ruby script with help of FEL mode. Generate SHA256 of public key using ruby script.Р”Р€. I have followedР’В steps as given by Instead of generating private key using openssl, I have used same private key as used by Please find key file.Р”Сћ.

Nice conversion regarding to secure boot for H3.Р”Р‡rom this reference, I am trying to enable secure boot in H6 SoC (Orange pi3).